1. Field of the Invention
The invention relates generally to the field of data transfer systems, and more specifically to transfer arrangements for transferring data in a digital data processing system. The invention provides a buffer system that buffers data transfers between a processor and memory, on the one hand, and an input/output system, on the other hand, which enables the efficient transfer of data therebetween.
2. Description of the Prior Art
A digital data processing system generally includes three basic elements; namely, a memory element, an input/output element, and a processor element, all interconnected by one or more busses. The memory element stores data in addressable storage locations. This data includes both operands and instructions for processing the operands. The processor element causes data to be transferred or fetched, to it from the memory element, interprets the incoming data as either instructions or operands, and processes the operands in accordance with the instruction. The results are then stored in addressed locations in the memory element. An input/output element also communicates with the memory element in order to transfer data into the system and to obtain the processed data from it. The input/output elements normally operate in accordance with control information supplied to it by the processor element. The input/output elements may include, for example, printers, teletypewriters or keyboards and video display terminals, and may also include secondary data storage devices such as disk drives or tape drives.
Buffers are often used to synchronize communications between the various elements in a data processing system. A buffer is a storage element containing one or more storage locations which receives data from one part "upstream" of the system, and transmits it to a "downstream" element. Bidirectional buffers also exist which can receive and transmit data in both directions.
Buffers are used for a number of reasons. In some cases, the units to which they are connected may be operating at different transfer speeds. The buffer may receive and store data at the timing speed of the transmitting device and transmit the stored data at the timing speed of the receiving device. In other cases, one unit may transfer data asynchronously (that is, using timing and control signals that are not synchronized to any periodic clocking signal), and the other unit may transfer data synchronously. The buffer communicates with each unit in its timing mode.
Buffers are also used between two units which operate at different operational speeds, particularly if it is desirable that data be available for a receiving unit without risk of delay by a slower transmitting unit or that there be a location in which the transmitting unit may place data if it can transmit the data faster than the receiving unit can accept and use the data. If a receiving unit requires data to be supplied to it at a specific rate, the transmitting unit can load some or all of the data being transferred into a buffer before beginning the transfer to a faster receiving unit. The receiving unit can then take data from the buffer. If the transmitting unit loads only some, but not all of the data in the buffer, it will have to load enough data to ensure that it can supply the rest of the data in the time required by the receiving unit.
Similarly, a faster transmitting unit can place some or all of the data into a buffer before the beginning of a transfer to a slower receiving unit. If the faster transmitting unit does not place all of the data into the buffer before the transfer, the buffer must be large enough to accommodate the slower data acceptance rate of the receiving unit throughout the transfer.
Buffers are often used in controllers or bus adapters of input/output devices. These input/output devices communicate through a controller or bus adapter with the memory element to transfer data for storage in the memory element or to receive data from the memory element for long-term storage in a disk or tape drive or printing or display on a video display terminal. The input/output devices also communicate with the central processing element to receive control information which enables the input/output device to perform an operation, and to transmit status information indicating the operating status of the device.
Data transfers between the input/output controllers on the one hand and the memory and processor, on the other hand, often occur in blocks of a selected maximum number of words, each of which is transferred during a transfer cycle over an input/output bus. For example, U.S. Pat. No. 4,232,366, issued to John V. Levy, et al, on Nov. 4, 1980, and entitled "Bus For A Data Processing System With Overlapped Sequences", discloses a bus in which transfers may occur in blocks of either one, two or three transfer cycles (ignoring the cycles in which acknowledgements are transmitted). In the first cycle, a command and address are transmitted. The command indicates in part, the number of words in the block. For example, if the command is a READ command, the command and address word is the only word in the block. If the command is a WRITE command, there are two words in the block, namely the command and address word, and a second word containing data to be written into the addressed location. Finally, if the command is an EXTENDED WRITE command, there are three words in the block, namely the command and address word, and two data words, one of which is written into the addressed location, and the other being written into the next higher addressed location. Generally, a controller or bus adapter is adapted to connect to a plurality of input/output devices several of which may be engaging in transfers to or from the memory and processor contemporaneously. While only one transfer can occur over a typical bus at a time, the memory and processor may be able to transfer data or control and status information with the controller at the same time that the input/output devices are transferring data with the controller. Prior buffering systems have provided but one buffer path through which all transfers were funnelled. This can slow down transfers among the various units in the system.